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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. TPSM82480 slvsdt1 ? july 2017 TPSM82480 5.5-v input, 6-a, step-down converter with integrated inductor 1 1 features 1 ? ultra small 7.9 x 3.6 x 1.5 mm power module ? output current of 6 a ? input voltage range 2.4 to 5.5 v ? output voltage range 0.6 to 5.5 v ? typical quiescent current of 23 a ? feedback voltage accuracy of 1% (pwm mode) ? output voltage select ? phase shifted operation ? automatic power save modes ? forced pwm mode ? adjustable soft start ? power good / thermal good outputs ? undervoltage lockout ? over-current and short-circuit protection ? over-temperature protection ? -40 c to 125 c operating junction temperature range 2 applications ? low profile point-of-load supply ? solid state drives ? ultra portable/tablet/embedded pc ? optical modules, cmos cameras ? wireless modules, network cards 3 description the TPSM82480 is a synchronous step-down dc-dc converter module for low profile point-of-load power supplies. the input voltage range of 2.4 to 5.5 v enables operation from typical 3.3-v or 5-v interface supplies as well as from backup circuits dropping down as low as 2.4 v. the output current is up to 6 a continuously provided by two phases of 3 a each. these run out-of-phase, reducing pulse current noise significantly. the TPSM82480 provides automatically entered power save modes to maintain high efficiency down to very light loads. this incorporates an automatic phase adding and shedding feature using both or only one phase according to the actual load. the pulse skip mode for very light loads can be switched off by using the mode feature. the device features a power good signal and an adjustable soft start. also, the device features a thermal good signal to detect excessive internal temperature. the output voltage can be changed to a preselected value by vsel pin. TPSM82480 is able to operate in 100% duty cycle mode. device information (1) part number package body size (nom) TPSM82480mop qfm (24) 7.90 3.60 x 1.55 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. space space typical application schematic efficiency vs output current, v in = 12 v advance information cout vout/6a r2 r1 rs ss/tr agnd pgnd vin1 vin2 2.4 to 5.5v 10f 10f TPSM82480 3.3nf mode vsel en pg tg r3 vout fb copyright ? 2017, texas instruments incorporated productfolder ordernow technical documents support &community tools & software
2 TPSM82480 slvsdt1 ? july 2017 www.ti.com product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings ............................................................ 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 electrical characteristics ........................................... 5 6.6 typical characteristics .............................................. 7 7 detailed description .............................................. 8 7.1 overview ................................................................... 8 7.2 functional block diagram ......................................... 8 7.3 feature description ................................................... 9 7.4 device functional modes ........................................ 10 8 application and implementation ........................ 12 8.1 application information ............................................ 12 8.2 typical application ................................................. 12 8.3 system examples .................................................. 22 9 power supply recommendations ...................... 22 10 layout ................................................................... 23 10.1 layout guidelines ................................................. 23 10.2 layout example .................................................... 23 11 device and documentation support ................. 24 11.1 documentation support ....................................... 24 11.2 receiving notification of documentation updates 24 11.3 community resources .......................................... 24 11.4 trademarks ........................................................... 24 11.5 electrostatic discharge caution ............................ 24 11.6 glossary ................................................................ 24 12 mechanical, packaging, and orderable information ........................................................... 24 12.1 package option addendum .................................. 25 4 revision history date revision notes july 2017 * initial release. advance information
3 TPSM82480 www.ti.com slvsdt1 ? july 2017 product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated 5 pin configuration and functions mop package 24-pin qfm pin functions pin i/o description name no. vout1 1 output voltage node phase 1 (master), must be connect with vout2 pgnd1 2, 3, 20,21 power ground phase 1 (master) vin1 4, 24 supply voltage phase 1 (master) en 5 enable input (high=enabled, low = disabled) pg 6 power good (open drain, requires pull-up resistor) vsel 7 output voltage select (high = vout2, low=vout1) , vout1 < vout2 tg 8 thermal good (open drain, requires pull-up resistor) mode 9 operating mode selection (low=automatic pwm/psm, high = forced pwm) vin2 10, 23 supply voltage phase 2 pgnd2 11,12, 14, 22 power ground phase 2 vout2 13 output voltage node phase 2, must be connected with vout1 ss/tr 15 soft-start / tracking. an external capacitor connected to this pin sets the output voltage rise time. agnd 16 analog ground fb 17 output voltage feedback for the adjustable version. connect resistive voltage divider to this pin. rs 18 resistor select. connect resistor that sets the level for the second output voltage here (activated by vsel= high) vo 19 vout detection (connect to vout, output discharge is internally connected to this pin) 12 3 4 10 5 67 8 9 15 16 17 18 19 20 14 13 12 11 21 24 23 22 32 1 20 14 19 18 17 16 15 9 8 7 6 5 4 10 11 12 13 24 21 22 23 topview bottomview advance information pin1 marker
4 TPSM82480 slvsdt1 ? july 2017 www.ti.com product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) all voltages are with respect to network ground terminal. 6 specifications 6.1 absolute maximum ratings min max unit pin voltage range (1) vin -0.3 6 v en, vsel, mode, ss/tr, pg, tg -0.3 6 v fb, rs -0.3 3 v power good / thermal good sink current pg, tg 10 ma operating junction temperature range, t j -40 150 c storage temperature range, t stg -65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001, all pins (1) 1000 v charged device model (cdm), per jedec specification jesd22-c101, all pins (2) 500 6.3 recommended operating conditions min typ max unit supply voltage range, v in 2.4 5.5 v output voltage range, v out 0.6 5.5 v maximum output current, i out 6 a operating junction temperature, t j ? 40 125 c (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . 6.4 thermal information thermal metric (1) TPSM82480 unit mop 24 pins jedec with thermal vias r ja junction-to-ambient thermal resistance 32.2 c/w r jc(top) junction-to-case (top) thermal resistance 13.6 c/w r jb junction-to-board thermal resistance 11.5 c/w jt junction-to-top characterization parameter 0.53 c/w jb junction-to-board characterization parameter 11.3 c/w r jc(bot) junction-to-case (bottom) thermal resistance - c/w advance information
5 TPSM82480 www.ti.com slvsdt1 ? july 2017 product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated 6.5 electrical characteristics over operating junction temperature range (t j = ? 40 c to 125 c) and v in = 2.4 v to 5.5 v. typical values at v in = 3.6 v and t j = 25 c (unless otherwise noted). parameter test conditions min typ max unit supply v in input voltage range v in rising 2.6 5.5 v v in falling 2.4 5.5 i q operating quiescent current en = high, v in 3 v, i out = 0 ma, device not switching, t j = -40 c to +85 c 23 38 a 100% mode operation 3.5 6.5 ma i sd shutdown current en = low ( 0.3 v), t j = -40 c to +85 c 0.5 18.5 a v uvlo undervoltage lockout threshold falling input voltage 2.2 2.3 2.4 v hysteresis 200 mv t sd thermal shutdown temperature pwm mode, rising junction temperature 160 c thermal shutdown hysteresis pwm mode 10 control (en, vsel, mode, ss/tr, pg, tg) v h input threshold voltage (en, vsel, mode) to ensure high level 1.2 v v l input threshold voltage (en, vsel, mode) to ensure low level 0.4 i lkg(en) input leakage current (en) en = v in or gnd 10 200 na i lkg(mode) input leakage current (mode, vsel) 10 200 na i ss/tr ss/tr pin source current 4.7 5.25 5.8 a v th(tg) thermal good threshold temperature pwm mode 120 c thermal good hysteresis pwm mode 10 v th(pg) power good threshold voltage rising (%v out ) 93% 96% 99% falling (%v out ) 89% 92% 95% v l(pg) output low threshold (pg, tg) i pg = -2 ma 0.4 v i lkg(pg) input leakage current (pg) 2 700 na i lkg(tg) input leakage current (tg) 2 100 na t ss internal soft-start time ss/tr = v in or floating 80 s t delay time from en rising until start switching 100 200 400 s power switch r ds(on) high-side mosfet on-resistance v in 3 v phase1 36 98 m phase2 low-side mosfet on-resistance phase1 29 72 m phase2 i lim high-side mosfet current limit per phase 4.3 5.0 5.8 a advance information
6 TPSM82480 slvsdt1 ? july 2017 www.ti.com product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) over operating junction temperature range (t j = ? 40 c to 125 c) and v in = 2.4 v to 5.5 v. typical values at v in = 3.6 v and t j = 25 c (unless otherwise noted). parameter test conditions min typ max unit (1) the output voltage accuracy in power save mode can be improved by increasing the output capacitor value, reducing the output voltage ripple. (2) for detailed information on output discharge see active output discharge . output v ref internal reference voltage 0.6 v i lkg(fb) input leakage current (fb) en = high v fb = 0.6 v 1 65 na i lkg(rs) input leakage current (rs) vsel = low, v rs = 0.6 v 1 65 na r rs internal resistance (rs to gnd) vsel = high, i rs = 1 ma 10 50 v out output voltage range v in v out 0.6 5.5 v v out feedback voltage accuracy pwm mode, v in v out + 1 v t j = ? 20 c to 85 c -1% 1% t j = ? 40 c to 125 c -1.4% 1.3% v out feedback voltage accuracy power save mode, l = 0.47 h, c out = 4 x 22 f (1) -1.4% 2.5% output discharge current (2) en = low, v out = 2.5 v 120 ma load regulation v out = 1.8 v, pwm mode operation 0.02 %/a line regulation 2.6 v v in 5.5 v, v out = 1.8 v, i out = 6 a, pwm mode operation 0.02 %/v advance information
7 TPSM82480 www.ti.com slvsdt1 ? july 2017 product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated 6.6 typical characteristics figure 2. quiescent current figure 3. shutdown current figure 4. high-side switch resistance figure 5. low-side switch resistance advance information
8 TPSM82480 slvsdt1 ? july 2017 www.ti.com product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated 7 detailed description 7.1 overview the TPSM82480 is a high efficiency synchronous switched mode step-down converter module based on a 2- phase peak current control topology. it is designed for smallest solution size low-profile applications, converting a 2.4 v to 5.5 v input voltage into a lower 0.6 v to 5.5 v output voltage. while an outer voltage loop sets the regulation threshold for the inner current loop, based on the actual v out level, the inner current loop regulates to the actual peak inductor current level for every switching cycle. the regulation network is internally compensated. while the on-time is determined by duty cycle, inductance and cycle peak current, the switching frequency of typically 2.2 mhz is set by a predicted off-time. the device features a power save mode (psm) to keep the conversion efficiency high over the whole load current range. the TPSM82480 is a 2-phase converter, sharing the load among the phases. identical in construction, the second phase control is connected with an adaptive delay to the first phase. both the phases use the same regulation threshold and cycle-by-cycle peak current setpoint. this ensures a phase-shifted as well as current- balanced operation. using the advantages of the 2-phase topology, a 6-a continuous output current is provided with high performance and as small as possible solution size. 7.2 functional block diagram space figure 6. TPSM82480 vin2 vin1 vout1 vout2 fb rs pg pgnd2 agnd pgnd1 en mode ss/tr vsel control logic thermal shutdown hs1 phase shift hs2 power control vin1 vin2 gate drive hs2 hs1 gm v ref gm out vsel off-timer t on2 t on1 delay vout power save mode pg control vo v ref tg tg control uvlo vin vin ocp hs1 hs2 vsel en copyright ? 2017, texas instruments incorporated advance information
9 TPSM82480 www.ti.com slvsdt1 ? july 2017 product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.3 feature description 7.3.1 enable / shutdown (en) the device starts operation, when vin is present and enable (en) is set high. since the boundary en thresholds are specified with 1.2 v for rising and 0.4 v for falling voltages, the typical vales are 0.85 v (rising) and 0.65 v (falling). the device is disabled by pulling en low. leaving the en pin floating is not recommended. 7.3.2 soft start (ss), pre-biased output the internal soft start circuit controls the output voltage slope during startup. this avoids excessive inrush current and provides an adjustable controlled output-voltage rise time. the soft start also prevents unwanted voltage drop from high impedance power sources or batteries. when en is set to start device operation, the device starts switching after a delay of typically 200 s and vout rises with a slope, controlled by the external capacitor which is connected to the ss/tr pin (soft start). leaving the ss/tr pin floating or connecting to vin provides internally set fastest startup with a soft start slope of about 80us. see application curves for typical startup operation. the device can start into a pre-biased output. in this case, the device starts switching, only when the internal set point for vout increases above the pre-biased voltage level. 7.3.3 tracking (tr) the device tracks an external voltage applied to the ss/tr pin. the fb voltage tracks the external voltage as long as it is below about 0.6v. above 0.6v the device goes to normal operation. if the voltage at the ss/tr pin decreases below about 0.6v, the fb voltage tracks again this voltage. see tracking for further details. 7.3.4 output voltage select (vsel) a resistive divider (vout to fb to agnd) sets the output voltage of the TPSM82480. providing a logic high level at the vsel pin, another resistor, connected between fb and rs pins is connected in parallel to the lower resistor of the divider. this sets a different higher output voltage and can be used for dynamic voltage scaling (see setting v out2 using the vsel feature ). if the vsel pin is set low, the device connects an internal pull down resistor to keep the internal logic level low, even if the pin is floating afterwards. the device disconnects the resistor, if the pin is set to high. 7.3.5 forced pwm (mode) to avoid power save mode (psm) operation , the device can be forced to pwm mode operation by pulling the mode pin high. in this case the device operates continuously with it's nominal switching frequency and the minimum peak current can go as low as -500 ma. if the mode pin is set low, the device connects an internal pull down resistor to keep the internal logic level low, even if the pin is floating afterwards. the device disconnects the resistor, if the pin is set to high. 7.3.6 power good (pg) the TPSM82480 has a built in power good function. the pg pin goes high, when the output voltage has reached its nominal value. otherwise, including when disabled, in uvlo or thermal shutdown, pg is low. the pg pin is an open drain output that requires a pull-up resistor and can sink typically 2ma. if not used, the pg pin can be left floating or grounded. 7.3.7 thermal good (tg) as long as the junction temperature of the TPSM82480 is below the thermal good temperature of typically 120 c, the logic level at the tg pin is high. if the junction temperature exceeds that temperature, the tg pin goes low. this can be used for the system to take action preventing excessive heating or even thermal shutdown. the tg pin is an open drain output that requires a pull-up resistor and can sink typically 2ma. if not used, the tg pin can be left floating or grounded. advance information
10 TPSM82480 slvsdt1 ? july 2017 www.ti.com product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) 7.3.8 active output discharge the vo pin, connected to the output voltage, provides an active discharge path when the device is switched off by setting en low or uvlo event. in case of being activated, this discharge circuit sinks typically 120ma for output voltages of typically 1 v and above. if v out is lower, the active current sink enters linear operation mode and the discharge current decreases. 7.3.9 undervoltage lockout (uvlo) the undervoltage lockout prevents misoperation of the device, if the input voltage drops below the uvlo threshold which is set to typically 2.3 v. the converter starts operation again once the input voltage exceeds the threshold by a hysteresis of typically 200 mv. 7.3.10 thermal shutdown the junction temperature (t j ) of the device is monitored by an internal temperature sensor. if t j exceeds 160 c (typical), the device goes in thermal shutdown with a hysteresis of about 10 c. both the power fets are turned off and the pg pin goes low. once t j has decreased enough, the device resumes normal operation with soft start. 7.4 device functional modes 7.4.1 pulse width modulation (pwm) operation the TPSM82480 is based on a predictive off-time peak current control topology, operating with pwm in continuous conduction mode for heavier loads. the switching frequency is typically 2.2mhz. both the master and follower phase regulate to the same vout level, each with a separate current loop, using the same peak current set point, cycle by cycle. this provides excellent peak current balancing, independent of inductor dc resistance matching. since the follower phase operates with an adaptive delay to the master phase, phase shifted operation is always obtained. if the load current decreases, the device runs with the master phase only (see phase add/shed and current balancing ). pwm only mode can be forced by pulling mode pin high. if mode is set low, the device features an automatic transition into power save mode, entered at light loads, running in discontinuous conduction mode (dcm). 7.4.2 power save mode (psm) operation as the load current decreases to half the ripple current, the converter enters power save mode operation. during psm, the converter operates with reduced switching frequency maintaining high conversion efficiency. power save mode is based on an adaptive peak current target, to keep output voltage ripple low. since each pulse shifts v out up, a pause time happens until v out trips the internal v out_low threshold again and the next pulse takes place. the switching frequency in psm (one phase operation) calculates as: space (1) 7.4.3 minimum duty cycle and 100% mode operation the minimum on-time, which is typically 70ns, normally determines a limit on the minimum operating duty cycle. the calculation is: space (2) space however, a frequency foldback lowers the switching frequency depending on the duty cycle and ensures proper regulation for every duty cycle. ]hz[ f % 100 ns 70 dc sw min = ( ) in 2 peak out in out out ) psm (sw v il v v v i2 f - = advance information
11 TPSM82480 www.ti.com slvsdt1 ? july 2017 product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated device functional modes (continued) there is no limit towards maximum duty cycle. when the input voltage becomes close to the output voltage, the device enters automatically 100% duty cycle mode and both high-side fets switch on as long as vout remains below the regulation setpoint. in this case, the voltage drop across the high-side fets and the inductors determines the output voltage level. an estimate for the minimum input voltage to maintain output voltage regulation is: space (3) space where the maximum dcr of the inductors is 27m . in 100% duty cycle mode, the low-side fets are switched off. the typical quiescent current in 100% mode is 3.5 ma. 7.4.4 phase shifted operation using an inherent benefit of the two-phase conversion, the two phases of TPSM82480 run out of phase. for every switching cycle, the second phase is not allowed to turn on its high-side fet until the master phase has reached its peak current value. this limits the input rms current and corresponding switching noise. 7.4.5 phase add/shed and current balancing when the load current is below the internal threshold, only the master phase operates. the second phase activates, if the load current exceeds the threshold of typically 1.7 a. the second phase powers off with a hysteresis of about 0.5 a, when the load current decreases. 7.4.6 current limit and short circuit protection each phase has a separate integrated peak current limit. the dc values are specified in the electrical characteristics . while its minimum value limits the output current of the phase, the maximum number gives the current that must be considered to flow in some operating case. at the peak current limit, the device provides its maximum output current. however, if the current limit situation remains for 512 consecutive switching cycles, the peak current folds back to about 1/3 of the regular limit. this limits the output power for over current and short circuit events. the foldback current limit is released to the normal one only if the load current has decreased as far as needed to undercut the (foldback) peak current limit. advance information ? ? w + + = m5.13 2 r i v v )on(ds out (min) out (min) in
12 TPSM82480 slvsdt1 ? july 2017 www.ti.com product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated 8 application and implementation space note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. space 8.1 application information the TPSM82480 is a switched mode step-down converter module, able to convert a 2.4-v to 5.5-v input voltage into a lower 0.6-v to 5.5-v output voltage, providing up to 6 a continuous output current. it needs a minimum amount of external components. apart from the output and input capacitors, additional resistors or capacitors are only needed to enable features like soft start, adjustable and selectable output voltage as well as power good and/or thermal good. 8.2 typical application space space figure 7. typical application using TPSM82480 for a 6a point-of-load power supply space 8.2.1 design requirements the following design guideline provides a range for the component selection to operate within the recommended operating conditions. table 1 shows the components selection that was used for the measurements shown in the application curves . advance information copyright ? 2017, texas instruments incorporated vout/6a r2 r1 vo fb rs ss/tr agnd pgnd1 pgnd2 vin1 vin2 vin 2.4 to 5.5v c2 c1 TPSM82480 c5 en mode vsel pg tg r3 vout2 vout1 r4 r5 pgnd v tg v pg pgnd c3/c4 c7/c8
13 TPSM82480 www.ti.com slvsdt1 ? july 2017 product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated typical application (continued) table 1. list of components reference description manufacturer power module 5.5-v, 6-a step-down module with integrated inductor TPSM82480mop, texas instruments c1, c2 2x22- f, 10-v, ceramic, 0603, x5r grm188r61a226me15#, murata c3, c4, c7, c8 4x22- f, 25-v, ceramic, 0805, x5r grm21br61e226me44l, murata c5 3300-pf, 10-v, ceramic, 0402 standard r1, r2, r3 depending on vout1 and vout2, chip, 0402, 0.1% standard r4, r5 470-k , chip, 0603, 1/16-w, 1% standard 8.2.2 detailed design procedure 8.2.2.1 setting the adjustable output voltage while the device regulates the fb voltage to 0.6v, the output voltage is specified from 0.6 to 5.5 v. a resistive divider (from vout to fb to agnd) sets the actual output voltage of the TPSM82480. equation 4 and equation 5 are calculating the values of the resistors. first, determining the current through the resistive divider leads to the total resistance (r 1 + r 2 ). a minimum divider current of about 5 a is recommended and can be higher if needed. space (4) (5) space 8.2.2.2 setting v out2 using the vsel feature a v out level, different as set with r 1 and r 2 (see setting the adjustable output voltage ), can be forced by connecting r 3 between fb and rs pins and pulling vsel high. r 3 is calculated using equation 6 . space (6) where: v 1 is the lower level output voltage and v 2 the higher level output voltage. space 8.2.2.3 output capacitor selection the recommended minimum output capacitance is 4 x 22 f, that can be ceramic capacitors exclusively. a larger value of c out might be needed for v out 1.8v, to improve transient response performance, as well as for v out > 3.3 v to compensate for voltage bias effects of the ceramic capacitors. the other way round, using of an additional feed forward capacitor can help reducing amount of output capacitance that is needed to achieve a certain transient response target (see table 3 ). the TPSM82480 provides a wide output voltage range of 0.6 v to 5.5 v. while stability is a critical criteria for the output filter selection, the output capacitor value also determines transient response behavior, ripple and accuracy of v out . the internal compensation is designed for an output capacitance range from about 50 f to 150 f effectively. since ceramic capacitors are used preferably, this translates into nominal values of 4 x 22 f to 4 x 47 f and mainly depends on the output voltage. the following values are recommended: ) r r( v v r 2 1 out ref 2 + = fb out 2 1 i v r r = + advance information )v v( for )r r r()v v( r r v r 1 2 22 2 1 1 2 22 1 1 3 > + - =
14 TPSM82480 slvsdt1 ? july 2017 www.ti.com product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated table 2. recommended output capacitor values (nominal) v out 1.0v 1.0v v out 3.3v v out 3.3v 2x22 f 4x22 f 4x47 f 6x47 f (1) the values in the table are nominal values. the effective capacitance can differ significantly, depending on package size, voltage rating and dielectric material. space beyond the recommendations in table 2 , other values can be chosen and might be suitable depending on vout and actual effective capacitance. in such case, stability needs to be checked within the actual environment. even if the output capacitance is sufficient for stability, a different value might be desirable to improve the transient response behavior. table 3 can be used to determine capacitor values for specific transient response targets: table 3. recommended output capacitor values (nominal) output voltage [v] load step [a] output capacitor value (1) feedforward capacitor (1) typical transient response accuracy mv % 1.0 0 - 3 4 x 47 f - 50 5 3 - 6 50 5 1.8 0 - 3 4 x 22 f 36pf 50 3 3 - 6 50 3 2.5 0 - 3 4 x 22 f 36pf 62 2.5 3 - 6 50 2 3.3 0 - 3 4 x 47 f 36pf 100 3 3 - 6 80 2.5 space the architecture of the TPSM82480 allows the use of tiny ceramic output capacitors with low equivalent series resistance (esr). these capacitors provide low output voltage ripple and are recommended. to keep its low resistance up to high frequencies and to get narrow capacitance variation with temperature, it is recommended to use x5r or x7r dielectrics. using even higher values than demanded for stability and transient response has further advantages like smaller voltage ripple and tighter dc output accuracy in power save mode. 8.2.2.4 input capacitor selection the input current of a buck converter is pulsating. therefore, a low esr input capacitor is required to prevent large voltage transients at the source but to provide peak currents to the device. the recommended value for most applications is 2 x 10 f, split between the vin1 and vin2 inputs and placed as close as possible to these pins and pgnd pins. if additional capacitance is needed, it can be added as bulk capacitance. to ensure proper operation, the effective capacitance at the vin pins must not fall below 2 x 5 f. low esr multilayer ceramic capacitors are recommended for best filtering. increasing with input voltage, the dc bias effect reduces the nominal capacitance value significantly. to decrease input ripple current further, larger values of input capacitors can be used. 8.2.2.5 soft start capacitor selection the soft start ramp time can be set externally connecting a capacitor between the ss/tr and agnd pins. the capacitor value c ss that is needed to get a specific rising time t ss calculates as: space (7) v6.0 a 25 .5 t c ss ss m d = advance information
15 TPSM82480 www.ti.com slvsdt1 ? july 2017 product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated space since the device has an internal delay time t delay from en=high to start switching, the overall startup time is longer as shown in figure 8 . figure 8. soft start t ss if very large output capacitances are used (e.g. > 4x47 f), the use of a soft start capacitor is mandatory to secure complete startup. 8.2.2.6 tracking for values up to 0.6v, an external voltage, connected to the ss/tr pin, drives the voltage level at the fb pin. in doing so, the voltage at the fb pin is directly proportional to the voltage at the ss/tr pin. when choosing the resistive divider proportion according to equation 8 , v out tracks v tr simultaneously. space (8) space figure 9. voltage tracking space ss/tr fb r1 r2 r3 r4 v tr v out TPSM82480 0v 0.6v copyright ? 2017, texas instruments incorporated 4 3 2 1 r r r r = advance information en v out pg 0 l h l h delay t d ss t d nom
16 TPSM82480 slvsdt1 ? july 2017 www.ti.com product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated following the example of setting the adjustable output voltage with v out = 1.8 v, r 1 = 240 k and r 2 = 120 k , equation 9 and equation 10 calculate r3 and r4, connected to the ss/tr pin. different to the resistive divider at the fb pin, a larger current must be chosen, to avoid a tracking offset caused by the 5.25 a current that flows out of the ss/tr pin. assuming a 250 a current, r 4 calculates as follows: space (9) space r 3 calculates now rearranging equation 8 : space (10) space however, the following limitations can influence the tracking accuracy: ? the upper limit of the ss/tr voltage that can be tracked is about 0.6v. since it is detected internally by a comparator, process variation and ramp speed can cause up to 30 mv different threshold. ? in case that the voltage at ss/tr ramps up immediately when vin is supplied or en is set high, the internal startup delay, t delay , delays the ramp of v out . the internal ramp starts after t delay at the voltage level, which is actually present at the ss/tr pin. ? the tracking down speed is limited by the rc time constant of the internal output discharge (always connected when tracking down) and the actual load with the output capacitance. note: the device tracks down with the same behavior for mode high (forced pwm) or low (auto psm). 8.2.2.7 thermal good the thermal good pin provides an open drain output. the logic level is given by the pull up source which can be vout. in this case, tg goes or stays low, when the device switches off due to en, uvlo or thermal shutdown. when using an independent source for the pull up logic, the logic behavior at shutdown differs, because the tg pin internally goes high impedance. as before, tg goes low when tg threshold is reached, but goes back high in the event of being switched off (e.g. thermal shutdown). w = w w w = = k8.4 k 120 k 240 k4.2 r r r r 2 1 4 3 w = m = k4.2 a 250 v6.0 r 4 advance information
17 TPSM82480 www.ti.com slvsdt1 ? july 2017 product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.2.3 application curves v in = 3.6 v, v out = 1.8v (r1 / r2 = 240 k / 120 k ), t a = 25 c, (unless otherwise noted) v out = 3.2 v figure 10. efficiency vs output current v out = 3.2 v figure 11. efficiency vs input voltage v out = 1.8 v figure 12. efficiency vs output current v out = 1.8 v figure 13. efficiency vs output voltage v out = 0.9 v figure 14. efficiency vs output current v out = 0.9 v figure 15. efficiency vs input voltage advance information
18 TPSM82480 slvsdt1 ? july 2017 www.ti.com product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 16. output voltage vs output current (load regulation) figure 17. output voltage vs input voltage (line regulation) v out = 0.6 v figure 18. maximum output current v out = 5.5 v figure 19. maximum output current v out = 2.5 v figure 20. switching frequency vs output current v out = 1 v figure 21. switching frequency vs output current advance information
19 TPSM82480 www.ti.com slvsdt1 ? july 2017 product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated v out = 1.8 v figure 22. startup into 3.3 v out = 1.8 v figure 23. startup into 0.3 v out = 2.5 v figure 24. output discharge v out = 1 v figure 25. output discharge figure 26. typical operation pwm i out = 50 ma figure 27. typical operation psm advance information
20 TPSM82480 slvsdt1 ? july 2017 www.ti.com product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 28. adding 2nd phase figure 29. shedding 2nd phase figure 30. load transient response (psm-pwm), load step 0 to 3 a c ff = 36 pf (nom) figure 31. load transient response (psm-pwm), load step 0 to 3 a figure 32. load transient response (pwm-pwm), load step 3 to 6 a c ff = 36 pf (nom) figure 33. load transient response (pwm-pwm), load step 3 to 6 a advance information
21 TPSM82480 www.ti.com slvsdt1 ? july 2017 product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated c ff = 36 pf (nom) figure 34. load transient response (pwm-pwm), load step 0 to 6 a i out = 10 a figure 35. current limit fold-back at overload v in = 5 v v out = 3.3 v figure 36. maximum ambient temperature (TPSM82480 evm) v in = 5 v v out = 3.3 v i out = 6 a figure 37. device temperature (TPSM82480 evm) advance information
22 TPSM82480 slvsdt1 ? july 2017 www.ti.com product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.3 system examples this section provides typical schematics for commonly used output voltage values. space space figure 38. a typical 1.8 v & 2.5 v, 6 a power supply space table 4. resistive divider values for different combinations of v out output voltage r1 r2 r3 2.5v and 3.3v 380k 120k 285k 1.2v and 1.8v 120k 120k 120k 0.9v and 1.0v 60k 120k 360k space 9 power supply recommendations the TPSM82480 is designed to operate from a 2.4-v to 5.5-v input voltage supply. the input power supply's output current needs to be rated according to the output voltage and the output current of the power rail application. 1.8v & 2.5v/6a 120k 240k vo fb rs ss/tr agnd pgnd1 pgnd2 vin1 vin2 vin 22f 22f TPSM82480 3.3nf en mode vsel pg tg 206k vout2 vout1 470k 470k pgnd v tg v pg pgnd 2x 22f 2x 22f copyright ? 2017, texas instruments incorporated advance information
23 TPSM82480 www.ti.com slvsdt1 ? july 2017 product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated 10 layout 10.1 layout guidelines a recommended pcb layout for the TPSM82480 dual phase solution is shown below. it ensures best electrical and optimized thermal performance considering the following important topics: - both v out1 and v out2 must be connected to build a common vout structure. - the input capacitors must be placed as close as possible to the appropriate pins of the device. this provides low resistive and inductive paths for the high di/dt input current. the input capacitance is split, as is the v in connection, to avoid interference between the input lines. - the v out regulation loop is closed with c out and its ground connection. to avoid pgnd noise crosstalk, pgnd is kept split for the regulation loop. if a ground layer or plane is used, a direct connection by vias, as shown, is recommended. otherwise the connection of c out to gnd must be short for good load regulation. - the fb node is sensitive to dv/dt signals. therefore the resistive divider should be placed close to the fb (and rs pin in case of using r 3 ) pin, avoiding long trace distance. for more detailed information about the actual evm solution, see slvuai6 . space 10.2 layout example space space figure 39. TPSM82480 board layout advance information vout r1 vin pgnd1 vout1 pgnd1 pgnd1 pgnd1 pgnd2 vout2 pgnd2 pgnd2 vin1 vin1 vin2 vin2 pgnd2 enpg vsel tg mode vo rs agnd ss/tr vb r3r2 c5 c1 c2 c3 c4 c7 c8 pgnd pgndpgnd
24 TPSM82480 slvsdt1 ? july 2017 www.ti.com product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated 11 device and documentation support 11.1 documentation support 11.1.1 related documentation for related documentation see the following: ? TPSM82480evm-bsr002 evaluation module user's guide , slvub57 11.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.4 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 11.5 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. advance information
TPSM82480 www.ti.com slvsdt1 ? july 2017 25 product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. pre_prod unannounced device, not in production, not available for mass market, nor on the web, samples not available. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. space (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti ' s terms " lead-free " or " pb-free " mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br) : ti defines " green " to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) space (3) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. space (4) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. space (5) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device space (6) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a " ~ " will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. important information and disclaimer: the information provided on this page represents ti ' s knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti ' s liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. 12.1 package option addendum 12.1.1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (3) msl peak temp (4) op temp ( c) device marking (5) (6) TPSM82480mopr preview qfm mop 24 3000 tbd cu nipdau level-1-260c-unlim ? 40 to 125 tbd TPSM82480mopt preview qfm mop 24 250 tbd cu nipdau level-1-260c-unlim ? 40 to 125 tbd advance information
26 TPSM82480 slvsdt1 ? july 2017 www.ti.com product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated 12.1.2 tape and reel information device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TPSM82480mopr qfm mop 24 3000 TPSM82480mopt qfm mop 24 250 reel width (w1) reel dimensions a0 b0k0 w dimension designed to accommodate the component lengthdimension designed to accommodate the component thickness overall width of the carrier tape pitch between successive cavity centers dimension designed to accommodate the component width tape dimensions k0 p1 b0 w a0 cavity quadrant assignments for pin 1 orientation in tape pocket quadrants sprocket holes q1 q1 q2 q2 q3 q3 q4 q4 reel diameter user direction of feed p1 advance information
27 TPSM82480 www.ti.com slvsdt1 ? july 2017 product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated device package type package drawing pins spq length (mm) width (mm) height (mm) TPSM82480mopr qfm mop 24 3000 TPSM82480mopt qfm mop 24 250 advance information tape and reel box dimensions width (mm) w l h
28 TPSM82480 slvsdt1 ? july 2017 www.ti.com product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated www.ti.com package outline c 1.75 max pick & place nozzle area 2x 2.01.8 6x 3.275 .000 symm 0 .000 symm 0 18x 1.475 10x 0.30.2 6x 1.351.15 4x 1.10.9 4x 2.32.1 18x 0.650.45 4x 0.650.45 4x 0.675 4x 1.875 1.55 max 4x 1.275 4x 1 4x 0.5 b 3.73.5 a 8.07.8 (0.05) typ qfm - 1.55 mm max height mop0024a quad flat module 4223492/b 06/2017 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. pin 1 id area 0.08 c seating plane 1 0.1 c a b 0.05 10 13 20 12 21 3 11 0.1 c a b 0.05 0.1 c a b 0.05 0.1 c a b 0.05 24 23 22 2 4 14 scale 2.300 scale 2.300 advance information
29 TPSM82480 www.ti.com slvsdt1 ? july 2017 product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated advance information www.ti.com example board layout 0.05 min all around .000 symm 0 .000 symm 0 4x ( ) 1.075 8x ( ) 1.075 ( ) 2 pads & 2 vias 0.675 4x ( ) 2.175 16x ( )0.3 4x ( ) 0.07 18x ( ) 1.475 ( ) 3.675 ( ) 2.875 4x ( ) 2.175 4x ( ) 1.575 4x ( ) 0.975 4x ( ) 0.375 4x ( )0.5 4x ( )1 4x ( ) 1.875 6x ( ) 3.275 4x ( ) 1.575 2x ( ) 2.513 4x ( ) 1.275 18x (0.55) 6x (1.25) 2x (1.9) 4x (1) 10x (0.25) 4x (0.55) 4x (2.2) ( 0.2) via typ (r0.05) typ qfm - 1.55 mm max height mop0024a quad flat module 4223492/b 06/2017 notes: (continued) 3. this package is designed to be soldered to thermal pads on the board. for more information, see texas instruments literature number slua271 (www.ti.com/lit/slua271). 4. vias are optional depending on application, refer to device data sheet. if any vias are implemented, refer to their locations shown on this view. solder maskopening metal under solder mask pad detail typical exposed metal land pattern example solder mask defined scale:15x 1 2 10 13 20 12 21 3 11 22 23 24 4 14
30 TPSM82480 slvsdt1 ? july 2017 www.ti.com product folder links: TPSM82480 submit documentation feedback copyright ? 2017, texas instruments incorporated advance information www.ti.com example stencil design 16x (0.52) 6x (1.17) 2x (1.7) 4x (0.95) pads 4, 10,14 & 20 8x (0.98) pads 21-24 10x (0.25) 10x (0.55) 4x (1.865) pads 21-24 (r0.05) typ 18x (1.475) 8x (0.675) 4x (0.685) 6x (3.275) 4x (1.875) pads 4,10,14 & 20 8x (0.5) qfm - 1.55 mm max height mop0024a quad flat module 4223492/b 06/2017 notes: (continued) 5. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. solder paste example based on 0.125 mm thick stencil printed solder coverage by area under package pads 1, 3, 11 & 13: 88% pads 4, 10, 14 & 20: 90% pads 2, 12 & 21-24: 84% scale:15x symm symm 1 2 10 13 20 21 3 11 22 23 24 4 12 14 solder mask edge, typ metal under solder mask typ exposed metal typ
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